In a conventional semiconductor memory device a plurality of memory elements are arranged in the transverse direction and vertical direction, in other words, arranged in a matrix. There is such a device wherein the drain regions of the memory elements lying transversely are connected with one another by means of a bit line, the gate electrodes of the memory elements lying vertically are connected with one another by means of a word line and the source regions of the memory elements are connected with one another by means of a source line. Writing of data in or reading out of data from a desired cell is performed by selecting a specific bit line and a specific word line with an input/output control circuit or the like.
In order to realize a higher integration of such a semiconductor memory device there is a need to make each memory element smaller or shorten the distance between adjacent bit lines and that between adjacent word lines.
FIG. 21 is a plan view showing a conventional semiconductor memory device. FIGS. 22 and 23 are sectional views taken along a line X--X and a line Y--Y, respectively in FIG. 21.
Referring to these figures, a source line SL through which source regions 102 lying between memory elements 101 are connected with one another ( one source region is common to any two elements adjacent thereto) is made of a diffusion layer. Hence, if the marginal edge of the source line SL overlaps the edge of a word line WL, a coupling ratio would vary. For this reason there is required to provide a margin M1 (refer to FIG. 21), which results in an increased distance between adjacent word lines between which the source line SL is interposed.
In addition, there is a need to provide an alignment margin M2 between a drain contact 104 and the word line WL (refer to FIG. 21) so as to prevent a short circuit between word line WL and bit line BL. This also results in an increased distance between word lines between which the drain contact 104 is interposed.
On the other hand, if a size of memory elements is made to be small, a gate electrode of each element becomes small and a capacitance C.sub.1 based on an interlayer insulating film 106 which is sandwiched between a floating gate 105 and a control gate electrode 107 also becomes small. Although a voltage is applied to the control gate electrode to operate the memory element, the voltage which contributes to the operation is a voltage applied to the floating gate. This voltage is subject to a coupling ratio, which is a relationship between the capacitance C.sub.1 based on the aforesaid interlayer insulating film 106 and a capacitance C.sub.2 based on a gate insulating film which is interposed between the floating gate 105 and a semiconductor substrate 10. That is, the coupling ratio is found from C.sub.1 /(C.sub.1 +C.sub.2). Therefore, the larger the value C.sub.1 relative to the value C.sub.2 increases, the larger the coupling ratio increases, hence, the more effectively the floating gate can be applied with a voltage. In order to obtain a larger coupling ratio, the floating gate 105 needs to be elongated in the direction perpendicular to the bit line BL. Accordingly, the floating gate becomes longer in such a direction than the width W of an active region. This also results in a problem of an increased distance between adjacent bit lines. Further, since the width W of the active region needs to be sufficiently large in a region where the drain contact is formed, it is impossible to make the width W smaller throughout the active region.
As described above, with the conventional configuration there is a limitation in high integration of a semiconductor memory device.